Channel reduction and time coincidence IBM PC board for PET

A channel-reduction and time-coincidence board has been designed for high-efficiency detection of photons in time coincidence in PET devices. The board comprises twenty 3D-Flow processors, each capable of executing up to 26 operations in a single cycle. These processors can execute programmable real-time algorithms that route messages from the parallel top processor input port or North, East, West, South LVDS serial input ports to the parallel bottom processor output port or North, East, West, South LVDS serial output ports and can execute sorting and coincidence-detection algorithms. The board has a memory buffer (up to 512 MBytes) to store the attenuation correction coefficients and for de-randomizing and buffering data flow. It has 32 pairs of LVDS differential inputs and two pairs of LVDS differential outputs. Several transmission protocols can be implemented, including PETLINK protocol. Two in-phase clocks at 20 MHz and 40 MHz (with PLL /spl times/8 = 320 MHz internal clock) are distributed so as to limit the maximum skew between the clock of any processor in the system to less than 40 ps. The circuits are implemented in FPGA, and full programmability is only dependent on the real-time algorithms downloaded into the processor program memory. The board is suitable for current PET with different detector types and for the 3D-CBS for best PET efficiency improvement. Typically sixteen 3D-Flow/spl trade/ DAQ boards are interfaced to one coincidence board.