A low power, wide dynamic range multigain signal processor for the SNAP CCD

A four-channel custom chip designed for reading out the CCDs of the SNAP satellite visible imager is presented. Each channel consists of a single-ended to differential converter followed by a correlated double sampler and a novel multi slope integrator. The output signal is differentially brought out of the chip by an output buffer. This circuit is designed to operate at room temperature for test purpose and at 140K, which will be the operating temperature. The readout speed is 100kHz. The 16-bit dynamic range is covered using 3 gains each with a 12 bit signal to noise ratio. The prototype chip, implemented in a 0.25 /spl mu/m CMOS technology, has a measured readout noise of 7/spl mu/V rms at 100kHz readout speed, a measured non-linearity of /spl plusmn/0.025% and a power consumption of 6.5mW.