Toward an integrated design methodology for fault-tolerant, multiple clock/voltage integrated systems

This paper describes a communication-centric design methodology that addresses the fundamental challenges induced by the emergence of truly heterogeneous systems-on-chip (SoCs). For such systems, the globally asynchronous design paradigm seems to be the most promising (if not the only) solution for providing an underlying substrate for cost-effective and power efficient on-chip communication among diverse, mixed technology IPs. Additional challenges are related to reliability and error resilience of on-chip communication architectures. The proposed on-chip communication methodology targets all levels of abstraction, from circuit, to microarchitecture and system-level by seamlessly integrating solutions for robust and efficient globally asynchronous communication among diverse IPs.