Constraint driven dual-rail PLA module generator with embedded 2-input logic cells

This paper describes design and development of a module generator which is based on a timing-driven design methodology. This generator uses a design constraint to achieve a flexible transistor sizing in a logic cell generation part. In addition, generated logic cells can be easily adapted to a layout generator. Almost all of these logic cells have two inputs. 2-input logic cells are embedded in place of conventional AND/OR planes. By using the 2-input logic cells, some classes of logic functions can be implemented in a smaller circuit area. Moreover, an HDL model generator is developed to create delay behavior models easily and quickly with precise timing parameters.