A new input switching scheme for a capacitive micro-g accelerometer

The design and implementation of a new input switching capacitive microaccelerometer interface circuit with /spl mu/g resolution is presented. The accelerometers were fabricated on 50 /spl mu/m thick silicon-on-insulator (SOI) substrates using a two-mask, dry-release and low temperature process. Fabricated devices were interfaced with a high resolution, low noise and low power switched-capacitor integrated circuit (IC) implemented in a 2.5V 0.25 /spl mu/m N-well CMOS process with the chip size of 0.5/spl times/1.3mm/sup 2/. The measured sensitivity is 0.45V/g and the output noise floor is 4.4/spl mu/g//spl radic/Hz at 150Hz. The total power consumption is 5mW.