A 0.11 /spl mu/m CMOS clocked comparator for high-speed serial communications

A differential comparator targeted at receiving 40 Gb/s signals and operating off a single 1.2 V supply was designed and fabricated in 0.11 /spl mu/m CMOS. It comprises a front-end sampler and a regenerative stage with a clocked buffer to achieve a narrow aperture time and a high toggle rate. The regenerative stage output buffer employs an impedance modulation technique based on switching of feedback gain to reduce the reset time while keeping the effective gain high. We confirmed comparator operation with BER less than 10/sup -12/ up to 32 Gb/s at a toggle rate of 8 GHz.