A 72mW CMOS 802.11a direct conversion receiver with 3.5dB NF and 200kHz 1/f noise corner

A direct conversion 802.11a receiver front-end including a synthesizer with quadrature VCO has been integrated in a 0.13 /spl mu/m CMOS process. The chip has an active area of 1.8mm/sup 2/ with the entire RF portion operated from 1.2V and the low frequency portion operated from 2.5V. Its key feature is a current driven passive mixer with a low impedance load that achieves a low 1/f noise corner. Measured noise figure is 3.5dB with a 1/f noise corner at 200kHz, and an IIP3 of -2dBm. The synthesizer DSB phase noise integrated over a 10MHz band is less than -36dBc. The front end reported here has one of the lowest power consumption and 1/f noise corner at 5GHz in pure CMOS ever reported so far.