Optimal MST-based graph algorithm on FPGA segmentation design

The FPGA is currently widely used in digital systems. Its routability has a close relationship with the physical architecture. The application of switches improves the flexibility of the nets to be routed. Too many switches, however, bring a great performance penalty because of their high resistance and capacitance. To balance routing flexibility and performance constraints, the graph matching-based algorithm was proposed to construct good segmentation designs (Y.-W. Chang et al., Proc. IEEE/ACM Int. Conf. on CAD, p.34-9, 1998; J.-M. Lin et al., Proc. ASP-DAC 2003, p.851-4, 2003). It attempts to maximize routability under performance constraints. During the execution of the algorithm, the paring scheme affects the outcome, so that the solution may not be optimal. We enhance the algorithm and present the MST-based graph algorithm. It is optimal for both row-based FPGAs and array-based FPGAs. The results are independent of the net merging order. We conducted experiments on ten sets of routing instances. The results show 4.31% reduction of net length from the matching-based algorithm to the MST-based algorithm.