An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes

In this abstract we present a highly manufacturable, high performance 90nm technology with best in class performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel stress and implant profile to generate enhanced performance with no additional masks. High drive currents of 1193uA/um and 587uA/um are obtained for nMOS and pMOS transistors respectively at 1.2V Vdd and an Ioff of 60nA//spl mu/m. An industry leading 90nm technology CV/I of 0.61 ps and 1.12ps are obtained for nMOS and pMOS transistors respectively. An aggressively scaled 12/spl Aring/ EOT plasma-nitrided, cluster gate dielectric is used. Process conditions are optimized to obtain high drive current, good Vt roll-off control and simultaneously meet reliability requirements.