Transistor optimization for leakage power management in a 65 nm CMOS technology for wireless and mobile applications

This paper presents a transistor optimization methodology tailored for wireless, digital consumer, and mobile applications that employ power management circuit techniques. This methodology is applied to a 65nm technology that supports a high-density (<0.5 um/sup 2/) embedded 6T SRAM cell. High performance logic (I/sub dn//I/sub dp/ = 550/300uA/um at L/sub poly/ = 39nm) and low leakage are achieved simultaneously by employing a data retention mode for the SRAM (I/sub leakage/ /spl sim/2pA/bit). Retention mode bias conditions and selective gate sizing in the SRAM reduces leakage by /spl sim/300X. Advanced transistor design including SSR channel, strain engineering, drain-extension (HDD) offset spacer, and HDD and halo profile optimization is used to achieve at least an additional 4/spl times/ reduction in leakage.