A low voltage to high voltage level shifter in a low voltage, 0.25/spl mu/m PD SOI process

This paper describes a low voltage to high voltage logic level shifter that has been designed entirely in a low breakdown voltage process. As such, the scalability of the design to higher output levels has not been restricted by the fabrication process used. Further, to increase the output voltage capability of the design, without altering the fabrication process in any way, the University of Idaho developed high voltage, laterally diffused MOSFET (LDMOSFET) is used for the output driver. By combining a unique circuit topology with LDMOSFETs, output voltage levels are achieved that exceed the breakdown voltage of the process used. A 2.5-5 volt implementation of the design is presented, along with a generalization for higher levels. All circuits have been developed in a 2.5 volt breakdown, 0.25/spl mu/, partially depleted, silicon-on-insulator, radiation hardened CMOS process.