DFF-drivers ICs for 40 Gb/s ETDM in InP DHBT technology

In this paper we present design and optimization of 40+ Gb/s ICs in the context of ETDM transmission. The integration of DFF and driver with 2/spl times/1.4V and 2/spl times/2V output swing is presented with a focus on driver design, optimization and swing/quality/power tradeoffs. Circuits were fabricated in a self-aligned InP DHBT technology. DFF-driver measurements at 40 Gb/s show that low power consumption drivers with extremely low added jitter were achieved.