A 2Gb/s 2-tap DFE receiver for mult-drop single-ended signaling systems with reduced noise

A 2Gb/s integrating 2-tap decision feedback equalizer receiver is implemented in a 0.25/spl mu/m CMOS process to reduce high- and low-frequency noise for multi-drop single-ended signaling system. Voltage margin is enhanced by 110%(90%) for a stubless channel at 2Gb/s (an SSTL channel at 1.2Gb/s).