A 1.6Gb/s/pin double-data-rate SDRAM with wave-pipelined CAS latency control

An 8M/spl times/32 graphic DOR (GDDR) SDRAM operating at 800MHz is introduced. It needs a large number of CAS latencies(CLs) to support the frequency range of 300 to 800MHz. A wave-pipelined CL control circuit is proposed to provide stable operation for the wide number of CLs. The gapless write-to-read scheme is applied to improve the efficiency of the data bus at high-speed operation with large number of CLs.