An 800MHz embedded DRAM with a concurrent refresh mode

The embedded DRAM employs a transfer gate formed from a 22A Gox, 1.5V logic IO device resulting in 3.2ns cycle and latency. A concurrent refresh mode and a refresh scheduler prove /spl ges/:99% memory availability for a 64/spl mu/s cell retention time. In-macro circuitry supports redundancy allocation during 800MHz multi-banking operation.