A fully integrated 0.13 /spl mu/m CMOS 10 Gb Ethernet transceiver with XAUI interface

A 10 Gb Ethernet transceiver chip integrated with 10 Gb/s serial and quad 3.125 Gb/s XAUI interfaces is implemented in 0.13 /spl mu/m CMOS and dissipates 898 mW from 1.2 V. A digital coarse control algorithm for VCOs reduced the VCO gains for noise immunity. A blind oversampling technique enabled synthesis of the XAUI interface.