Xpipes: a network-on-chip architecture for gigascale systems-on-chip

The growing complexity of embedded multiprocessor architectures for digital media processing will soon require highly scalable communication infrastructures. Packet switched networks-on-chip (NoC) have been proposed to support the trend for systems-on-chip integration. In this paper, an advanced NoC architecture, called Xpipes, targeting high performance and reliable communication for on-chip multi-processors is introduced. It consists of a library of soft macros (switches, network interfaces and links) that are design-time composable and tunable so that domain-specific heterogeneous architectures can be instantiated and synthesized. Links can be pipelined with a flexible number of stages to decouple link throughput from its length and to get arbitrary topologies. Moreover, a tool called XpipesCompiler, which automatically instantiates a customized NoC from the library of soft network components, is used in this paper to test the Xpipes-based synthesis flow for domain-specific communication architectures.