Silicon spike-based synaptic array and address-event transceiver

An integrated array of 2,400 spiking silicon neurons, with reconfigurable synaptic connectivity and adjustable neural spike-based dynamics, is presented. At the system level, the chip serves as an address-event transceiver, with incoming and outgoing spikes communicated over an asynchronous event-driven bus. Internally, every cell implements a spiking neuron that models general principles of synaptic operation as observed in biological membranes. Synaptic conductance and synaptic reversal potential can be dynamically modulated for each event. The implementation employs mixed-signal charge-based circuits to facilitate digital control of system parameters and minimize variability due to transistor mismatch. In addition to describing the structure of the silicon neurons, we present experimental data characterizing the operation of the 3mm /spl times/ 3 mm chip fabricated in 0.5 /spl mu/m CMOS technology.