FPGA based accelerator for functional simulation

We introduce an FPGA-based approach to accelerate functional simulation. We achieve speedups between 5 and 100X over pure software simulation. This approach takes advantage of a simulator's software procedural interface, provided by a commercial VHDL simulator. Our approach uses the master-slave co-simulation technique. The master is the HDL simulator, which controls the time advance mechanism. The slave is an FPGA board, where the DUT is synthesized in hardware. In the middle, we developed a communication library responsible for communicating the flow of events and values between both sides.