A novel FPGA architectural implementation of pipelined thinning algorithm

Thinning is a very important operation in the image preprocessing stage of pattern recognition. This investigation presents an improved thinning algorithm and its FPGA architectural implementation. The improved algorithm based on parallel pipelined design is adapted and formulated such that it is suitable to computing architecture implementation. The FPGA-based architecture extends the applicability of this algorithm in the area of real time image processing. Using the proposed Modification Unit Array, this work performs thinning operation within 0.07 sec at 40 MHz for a 512/spl times/512 picture.