Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage

A sleep switch dual threshold voltage domino logic circuit technique for placing idle domino circuits into a low leakage state is proposed in this paper. The circuit technique reduces the leakage energy by up to 830 times as compared to a standard low threshold voltage domino logic circuit in a 0.18 /spl mu/m CMOS technology. The sleep switch circuit technique significantly enhances the effectiveness of a dual threshold voltage CMOS technology to reduce subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. The circuit technique reduces leakage energy by up to 714 times as compared to a standard dual threshold voltage domino logic circuit. A domino adder enters and leaves the low leakage sleep mode within a single clock cycle. The energy overhead of the circuit technique is low, justifying the activation of the proposed sleep scheme by producing a net savings in total power consumption during idle periods as short as 57 clock cycles.