FPGA-based 3D median filtering using word-parallel systolic arrays

A 3D median filter architecture suitable for FPGA implementation is presented. The architecture consists of an ordered semi-systolic array of size equal to the filter window size. The hardware requirements of the architecture are significantly lower than those of previously reported systolic array architectures, making it desirable for the implementation of filters with large kernel sizes. An implementation of a 3/spl times/3/spl times/3/spl times/ filter in an Altera EP1C3T100C6 FPGA achieved a clock rate in excess of 100 MHz, being able to process a 128/spl times/128/spl times/128 image in 0.2 seconds. An implementation of a 3/spl times/3 2D filter achieved a clock rate in excess of 130 MHz.