An IF-sampling timing skew-insensitive parallel S/H circuit

An IF-sampling parallel S/H circuit is presented. The S/H employs timing skew-insensitive structure using a common sampling switch between two parallel channels. To achieve high sampling linearity the circuit utilizes bootstrapped input switches with a floating bulk and a bottom-plate sampling. A two-stage BiCMOS opamp provides a high DC gain and a wide bandwidth. Simulations give the SFDR of 76 dB with 207.2 MHz, 4 V/sub pp/ differential input signal. The S/H is designed in 0.35-/spl mu/m BiCMOS (SiGe) and consumes 320 mW from a 3.0 V supply. The S/H circuits have been implemented as a front-end of the parallel pipeline ADC.