A low-voltage CMOS low-dropout regulator with enhanced loop response

A 1.5-V 100-mA CMOS low-dropout regulator with a double pole-zero cancellation scheme and a linearly operated power PMOS transistor at dropout to enhance the loop-gain response, is presented. The circuit realization is well-studied and developed with respect to the loop-gain response, the transient response, the output noise and the output accuracy, as well as the standby power consumption. Implemented in a 0.6 /spl mu/m CMOS process, experimental results show that the regulator provides a full load transient response of less than 1-/spl mu/s settling time and less than 50-mV overshoots and undershoots. Moreover, it provides a ripple rejection of better than -26 dB and an output noise of 0.07 /spl mu/V/sqrt Hz at 100 kHz.