Self calibrated pipelined analog-to-digital converter for video rate applications

This paper concerns the design and simulation of a 10 bits video rate pipelined analog-to-digital converter. A self calibration mechanism is proposed for compensating any errors caused by tolerance of capacitors, which is common in CMOS analog circuits. A 1.5 bits per stage architecture is chosen and digital correction on the binary output is performed. A switched capacitor circuit is used as the main stage with offset compensation where necessary. Simulation is performed using a CMOS 0.8/spl mu/m technology model. At a sampling rate of 6.75MSPS, an INL and a DNL of 13.5LSB and 16 LSB were achieved, respectively.