Advances in wafer level and chip scale packaging

Wafer-level packaging (WLP) is becoming more prevalent in the semiconductor packaging industry, fuelled by the increasing prominence of area array devices employed in electronics manufacturing. With feature size requirements in the range of 10-15 /spl mu/m, the current thinking is that the bumping process should be accomplished by either a stepper or proximity mask aligner. A key factor in this decision is the financial investment of the manufacturer and the relative process benefits of photolithography. This paper presents the benefits of utilizing projection stepper technology in the wafer bumping process. In particular, the paper discusses an innovative system design that significantly improves stepper yields while enabling the imaging of thick resists on wafers. Considered are the relative performance capabilities and process flexibility of the system design versus conventional steppers and projection aligners. Described are key subsystems incorporated in the advanced stepper platform, including dual wafer handling, optimized lens field projection optics, and broadband illumination. The paper concludes that the resulting increase in throughput and process latitude can be expected to reduce cost of ownership (COO) when process and maintenance costs are considered as well as the initial capital expense of the equipment.