A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter

In this paper a CMOS image sensor with on-pixel analog-to-digital converter based on PWM scheme is proposed. The digital pixel sensor includes a novel digital circuit which allows to configure the internal 8-bit memory as a 4-bit counter/memory, so as to reduce the data bit lines routed to each pixel form 8-bit to 4-bit. Hence the total parasitic capacitance as well as power consumption associated with the switching activities of the global data bus lines are reduced. Besides 8-bit precision, the imager can also be configured to 4-bit precision for low resolution frame rate and decreasing overall power consumption. A prototype chip was realized in Alcatel 0.35/spl mu/m CMOS technology. Each pixel occupies an area of 46/spl mu/m x 48/spl mu/m with a fill-factor of 14%.