Reliability model and implementation for EEPROM emulation using flash memory

EEPROM emulation techniques are used with block-erasable Flash memories for embedded applications requiring nonvolatile storage of data that is updated in byte or word granularity. In this paper, we discuss the reliability of the emulated EEPROM using Flash memories. The reliability depends on many factors, including the emulation scheme, the EEPROM targets, and the Flash architecture used. Achieving reliability targets is a process of matching these factors with the endurance and data retention characteristics of the Flash technology. We present a model for combining parameters of emulation implementations with technology capability that can be used to predict reliability of the emulated EEPROM. This model enables selection of optimal layout of Flash blocks for emulation to meet a given EEPROM reliability target.