Enhanced ESD protection robustness of a lateral NPN structure in the advanced CMOS

This paper describes a novel, more robust design of a lateral snapback structure for use as ESD protection device in the state of the ail CMOS. It is shown that the device has significantly increased (/spl sim/100% in the investigated 9nm technology) ESD failure levels over the widely used grounded gate NMOS (ggNMOS). This is attributed to the absence of gate oxide breakdown, which is the dominant failure mode in the! classical ggNMOS structure in the advanced CMOS. In addition, the device design inhibits lower junction capacitance and allows straightforward MOSFET integration that favours its ESD protection application in the highspeed I/Os.