Stress-induced voiding in multi-level copper/low-k interconnects

Stress-induced voiding phenomenon in vias at different metallization layers was studied in details with stress temperatures ranging from 150/spl deg/C to 300/spl deg/C. At 1000-hour of stress migration (SM) test, the percentage change in the resistance showed that the thermally induced stress in the vias increased with increasing metallization layers. Furthermore, the vias at the edge of the wafer were more sensitive to the thermally induced stress than that at the center of the wafer. As such, more stress-induced damaged vias were observed at the upper metallization layers and at the edge of the wafer. These phenomena were attributed to the accumulated compressive stress experienced by the wafer with each increasing metallization layer and the poorer diffusion barrier coverage at the edge of the wafer due to the nature of physically vapor deposition (PVD) process. Some strategies such as the implementation of a resputtering step during the PVD process of the diffusion barrier layer and the design of dual-via interconnect were demonstrated to be effective in managing the stress-induced voiding effect in Cu interconnects. It was also proven that re-sputtering step during the PVD process of the diffusion barrier layer was necessary when Cu was integrated with dielectric of lower constant values because of its stronger dependency on process.