Novel 2-D RESURF LDMOSFET in 0.6 /spl mu/m CMOS technology for power ICs

A 0.6 /spl mu/m CMOS process was adapted to incorporate LDMOS transistors for Power Integrated Circuit Applications. The design was realised by adding only three additional ion implants process steps and one extra masking process step providing a cost effective approach. The design was optimised prior to manufacture by the Avanti TCAD simulation tool. Physical results show good agreement with the simulated device and display 2-D RESURF action.