An array cell transistor test structure for the leakage current analysis of stacked capacitor DRAMs with diagonal cell scheme

A new test structure for a stacked capacitor DRAM cell transistors with a diagonal active-area was developed to analyze the leakage current characteristics of the cell transistors. The leakage current components of the low power DRAMs with different retention fail distributions was investigated in detail using the test structure, and the important aspect of the sub-threshold leakage component was discussed for below 0.11 /spl mu/m DRAM cell transistors.