SPER junction optimisation in 45 nm CMOS devices

Ultra-shallow junction formation by solid phase epitaxial regrowth (SPER) has been shown to produce excellent junction profiles beyond that of conventional spike annealing. However residual damage can degrade various aspects of the transistor performance, annihilating any:improvement due to the junction profile. In this work we look at optimizing the junction and channel conditions to meet the dopant profile and transistor requirements for the 45 nm CMOS node. We show how an optimised junction implant and low temperature SPER spike anneal can further increase the activation level and profile of the junction. In devices we show results on the effect of SPER processing on both the substrate and gate doping. This includes junction overlap, channel deactivation, contact resistance, junction leakage, poly depletion, and gate leakage. We address each of these concerns for both pMOS and nMOS and identify what are the main strengths and weaknesses of SPER in devices.