SAP: design of a systolic array processor for computation in vision

The design and implementation of SAP chip, a systolic array processor for computations in vision, is described. The chip can be used to implement the Gaussian filter, the Laplacian of the Gaussian filter, and scale space generation. The architecture is based on an algorithm that can provide speeds an order of magnitude higher than the speeds of other systems previously proposed. The algorithm utilises the three properties of Gaussian: symmetry, separability, and scaling. The algorithm and the architecture exploit a high degree of pipelining and parallelism in order to obtain high speed, efficiency, and throughput. The architecture is adaptable for masks of any size, and the weights are not restricted to powers of two. The processor was designed using CMOS technology, fabricated, and tested. The chip is fully functional and operates at a rate of 10 MHz.<
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