A class of close-to-optimum adder trees allowing regular and compact layout

Wallace trees are well known for the design of the theoretically fastest multioperand adder. However, their complex interconnections can hardly give access to a practical implementation. The authors present a family of overturned-stairs trees which attain the same performance as that of Wallace trees in most useful cases, but require simple and regular interconnection schemes. These trees can be designed in a systematic way and laid out regularly in VLSI. A comparison is made between various trees to provide useful indexes for a practical design.<
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