Implementation of a reconfigurable architecture

Implementation of a reconfigurable architecture for an UTRA-TDD mobile terminal receiver is described. The architecture consists of a variable length digital channel filter and a variable word length pipeline ADC. The lengths depend on in-band and out-of-band power ratios. The architecture is power efficient and only consumes minimum power to meet the signal to noise ratio of the system. An average poker consumption of 13.3 mW has been recorded.