FPGA bridging fault detection and location via differential I/sub DDQ/

Standard I/sub DDQ/ testing is limited by the ability to distinguish a small fault current from a large background leakage current: this limitation is overcome in FPGAs by differential I/sub DDQ/ testing. Partitioning of interconnects further increases the detectability of a fault current. Fault location can be achieved by iteratively applying partitioned differential I/sub DDQ/ testing to eliminate fault-free nets. The location algorithm, easily automated, requires very few configurations and I/sub DDQ/ measurements, logarithmic to the number of initially-suspected faulty nets.