Simple and fast fractal image compression for VLSI circuits

Nowadays fractal image coding is performed by several methods focused to reduce the number of comparisons. This work describes a simple and fast method of fractal image compression for applications in mobile communications. The method uses a quadtree scheme on multiple levels of image resolution and the fractal coding is applied taking advantage of the multiresolution decomposition. The method uses a simple scheme of blocks classification into each resolution level on a pyramidal decomposition according to size and the intensity variation level of every block. The simplicity and regularity of the method make it suitable to be implemented on programmable logic devices, such as FPGAs, or in custom VLSI integrated circuits. The method can be implemented in parallel, saving up to three orders in the number of necessary operations to codify the image, reducing the asymmetry of the coding time compared with the decoding time.