Design of DCT/spl I.bar/2D toward FPGA

Long term objective is to conceive a system on chip of the JPEG coding chain. This article presents the VHDL specification, simulation and also synthesis results, of the two-dimensional discrete cosine transform DCT/spl I.bar/2D, which constitutes the first block of the JPEG chain. For that, we kept LOEFLER's algorithm which is the best for the DCT implementation, according to a comparison with other architectures. And we targeted the FPGAs as integration technology. Besides, seeing that the DCT is separable as transformation, the two-dimensional discrete cosine transform (DCT/spl I.bar/2D) can be formed by two one-dimensional discrete cosine transform (DCT/spl I.bar/1D).