Influence of surface treatment prior to ALD high-/spl kappa/ dielectrics on the performance of SiGe surface-channel pMOSFETs

Compressively strained Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFETs with atomic layer deposition (ALD) Al/sub 2/O/sub 3//HfO/sub 2//Al/sub 2/O/sub 3/ nanolaminate and low-pressure chemical vapor deposition p/sup +/ poly-SiGe gate electrode were fabricated. Surface treatment with either hydrogen fluoride (HF) clean, or HF clean followed by water rinse was performed prior to the ALD processing. The devices with water rinse show a good control of interfacial layer and device reproducibility, while the devices without water rinse lack a clearly observable interfacial layer and show scattered electrical characteristics and distorted mobility curve. A /spl sim/20% increase in hole mobility compared to the Si universal mobility and a /spl sim/0.6-nm-thick continuous interfacial layer are obtained for the pMOSFETs with water rinse.