FPGA implementation of radix 2 division with over-redundant quotient selection

The flexibility of field programmable gate arrays (FPGAs) can provide arithmetic intensive applications with the benefites of custom hardware but without the high cost of custom silicon implementations. In this paper present the adaptation of radix 2 division algorithm for lookup table based FPGAs implementation. This division algorithm is well suited for IEEE 754 standard operands belonging to the range. The implementation has been done with xilinx technology and FPGA-Advantage CAD tools.