A delay-locked frequency synthesizer with low phase noise performance

This paper presents a delay-locked frequency synthesizer implemented in 0.18 /spl mu/m CMOS technology. Symmetrical structures were employed in the circuit to reduce the inter-period jitter and phase noise. With the reference signal from an RF generator, the measured phase noise performance is of -105.5 dBc/Hz at 10 kHz offset with the carrier frequency of 2.07 GHz.