A multi-gigabit CMOS serial link transceiver using jitter tolerant Delay Locked Loop

A multi-gigabit CMOS serial link transceiver is described. To reduce the jitter of the clock, it uses a multiphase Delay Locked Loop(DLL) when it receives the serialized data. The circuit operates with a parallel sampling technique to reduce the speed requirements of the circuits. The analog phase detector provides a linear characteristic while deserializing the data with no phase offset. The proposed circuit is designed using 0.25 /spl mu/m CMOS technology. It is capable of recovering data at a speed of 2.5 Gbps.