New cost-effective VLSI implementation of a 2-D discrete cosine transform and its inverse

This paper first reviewed the two-dimensional discrete cosine transform (2-D DCT) and inverse DCT (IDCT) architectures. Then a new VLSI architecture, namely the transpose free row column decomposition method (TF-RCDM), for 2-D DCT/IDCT is proposed. The new RCDM architecture replaces the transpose circuits with permutation networks and parallel memory modules. As results, the timing overhead of I/O operations is eliminated and the hardware complexity is largely reduced. An accuracy testing system is designed to find the optimum word-length parameters. Based on the accuracy testing system, the proposed architecture has achieved the smallest word-length among the reported 2-D DCT architectures. Synthesis results showed that with 0.25-/spl mu/m CMOS technology library, the area was about 1.5 mm/sup 2/ and the speed was about 125 MHz.