Seamless top-down flow for quick trial of HW/SW co-design

A design flow implementing a whole embedded system from the system-level C description to field-programmable devices is described. In this design flow, system-level models are seamlessly implemented and verified, thus turnaround time for system-level design and implementation is reduced, compared with the conventional design flow. As examples, this design flow is applied to two target architectures; as general-purpose processor core and a configurable processor core.