Fully compatible integration of high density embedded DRAM with 65nm CMOS technology (CMOS5)

65 nm node SoC technology has been achieved to show good yield of 8 Mbit DRAM ADM using tapered BF/sub 2/ implantation without an additional mask step, the cell size of which is 0.11 /spl mu/m/sup 2/, with 3 layers of hybrid low-k material, SiLK/BD/BLOk, and Cu integration.