Scalability of strained silicon CMOSFET and high drive current enhancement in the 40 nm gate length technology

In this work, we investigated the scalability of strained Si technology. The impact of scaling source/drain length (L/sub SD/) on electrical characteristics was studied for the first time. Drive current enhancement of strained PMOSFET usually disappears as L/sub SD/ is scaled down due to the stress induced by shallow trench isolation (STI). However, it is demonstrated that with an optimized fabrication process, PMOSFET drive current can be improved by 11% for a feature size of 40 nm gate length and small L/sub SD/ (240 nm). In addition, ring oscillator propagation delay is improved by 18%, which clearly supports the scalability of strained Si devices for future LSI.