Modeling and optimization of substrate resistance for RF-CMOS

A predictive, physically based substrate resistance model for CMOS transistors operating at radio frequencies (RF) is described. This analytical model is scalable with transistor size and layout geometry. Measurement results confirm that the model accurately predicts the effect of substrate resistance on the transistor output impedance up to 20 GHz, including gate and drain bias dependencies. Minimization of the substrate resistance can be achieved by using substrate tap rings with small spacer distances and short finger widths.