Evaluation of fully-integrated switching regulators for CMOS process technologies

In this paper, we examine the feasibility of fully integrated voltage regulator for the power-optimized system-on-chip (SoC). The challenges and tradeoffs in designing fully-integrated buck switching regulators in CMOS process are described and a compact macro-power-model of a regulator is created. Optimization using geometric programming finds the optimal active and passive device sizes of on-chip regulator for highest efficiency in current and future process technologies. A fully-integrated switching regulator is designed and fabricated in a 0.35-/spl mu/m CMOS process to validate our modeling. The model is extrapolated to emerging CMOS technologies to show that >70% efficiency is possible.