Bit-error-rate performance of intra-chip wireless interconnect systems

This Letter evaluates the bit-error rate (BER) performance of a coherent binary phase-shift keying interconnect system operating on an intra-chip wireless channel at 15 GHz. Results show that the system performance degrades with the separation distance and the data rate. A high data rate at 2 Gb/s with a low BER<10/sup -5/ over the entire chip of size 20 /spl times/ 20 mm can be achieved with the transmitted power of 10 dBm.